1. Shodhganga@INFLIBNET
  2. SASTRA University
  3. School of Electrical and Electronics Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/90055
Title: Test pattern compression for low power system on chip soc design testing
Researcher: Saravana, S
Guide(s): Har Narayan Upadhyay
Keywords: Performance computing devices power management
switching activity reduces the power consumption
University: SASTRA University
Completed Date: 31/10/2014
Abstract: Abstract Included newline
Pagination: xix, 94p
URI: http://hdl.handle.net/10603/90055
Appears in Departments:School of Electrical and Electronics Engineering

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01_tittle.pdfAttached File22.81 kBAdobe PDFView/Open
02_certificate.pdf10.33 kBAdobe PDFView/Open
03_declaration.pdf11.9 kBAdobe PDFView/Open
04_dedicated.pdf9.23 kBAdobe PDFView/Open
05_acknowledgements.pdf17.05 kBAdobe PDFView/Open
06_table_of_contents.pdf18.38 kBAdobe PDFView/Open
07_list_of_tables.pdf15.79 kBAdobe PDFView/Open
08_list_of_figures.pdf14.04 kBAdobe PDFView/Open
09_list_of_acronyms.pdf14.58 kBAdobe PDFView/Open
10_abstract.pdf22.02 kBAdobe PDFView/Open
11_chapter_01.pdf56.02 kBAdobe PDFView/Open
12_chapter_02.pdf59.33 kBAdobe PDFView/Open
13_chapter_03.pdf112.12 kBAdobe PDFView/Open
14_chapter_04.pdf120.19 kBAdobe PDFView/Open
15_chapter_05.pdf104.99 kBAdobe PDFView/Open
16_chapter_06.pdf15.25 kBAdobe PDFView/Open
17_references.pdf44.75 kBAdobe PDFView/Open
18_list_of_publications.pdf15.69 kBAdobe PDFView/Open
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