Development, simulation & implementation of new strategies for power control and routing protocols for wireless Ad-hoc network

Abstract

Route construction should be done with a minimum of power usage and bandwidth consumption. An intelligent routing strategy is required to efficiently use the limited resources while at the same time being adaptable to the changing network conditions such as: network size, traffic density and network partitioning. Due to nodes mobility, the efficiency of a dynamic ad hoc routing protocol depends highly on updating speed of network topology changes. To achieve continuous updated routing tables, the nodes periodically broadcast short Hello messages to their neighbors. AODV is a reactive protocol it uses these periodic HELLO messages to inform the neighbors that the link is still alive. The HELLO messages will never be forwarded because they are broadcasted with Time To Live (TTL) = 1. When a node receives a HELLO message it refreshes the corresponding lifetime of the neighbor information in the routing table. The standard protocols use fixed specified values for the parameters. Main objective of the research work is to explore possibility and effect of changing parameter values to improve the performance of the routing protocol for power control. Soft computing differs from conventional (hard) computing in that, unlike hard computing, it is tolerant of imprecision, uncertainty, partial truth, and approximation. In effect, the role model for soft computing is the human mind. New strategies are proposed for routing protocol and power control based on the controlling Hello Interval parameter of AODV routing protocol. The adaptive value of Hello interval is decided by soft computing techniques viz. Fuzzy Inference System, Artificial Neural Network, Adaptive Neuro Fuzzy Inference System and Genetic algorithm. Effect of application of GA for ANN training has been studied. Proposed strategies employing soft computing are simulated using development support tools such as: MATLAB/SIMULINK/TRUETIME and NS2/Qualnet etc. Hardware Implementation has done on XCV5LX110T FPGA evaluation platform using Xilinx ISE Design 13.1.