Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/72468
Title: | Design validation and FPGA implementation of multistage telecommunication networks in HDL environment |
Researcher: | Kumar, Adesh |
Guide(s): | Kuchhal, Piyush and Singhal, Sonal |
Keywords: | Design FPGA implementation HDL environment |
University: | University of Petroleum and Energy Studies (UPES) |
Completed Date: | 2014 |
Abstract: | Abstract available newline |
Pagination: | 201p. |
URI: | http://hdl.handle.net/10603/72468 |
Appears in Departments: | Department of Electrical Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 106.58 kB | Adobe PDF | View/Open |
02_certificate.pdf | 102.83 kB | Adobe PDF | View/Open | |
03_acknowledgements.pdf | 84.43 kB | Adobe PDF | View/Open | |
04_curriculam vitae.pdf | 120.52 kB | Adobe PDF | View/Open | |
05_abstract.pdf | 86.85 kB | Adobe PDF | View/Open | |
06_summary.pdf | 96.32 kB | Adobe PDF | View/Open | |
07_contents.pdf | 87.12 kB | Adobe PDF | View/Open | |
08_list of figures.pdf | 101.28 kB | Adobe PDF | View/Open | |
09_list of tables.pdf | 93.9 kB | Adobe PDF | View/Open | |
10_acronyms.pdf | 94.57 kB | Adobe PDF | View/Open | |
11_list of abbrevations.pdf | 82.17 kB | Adobe PDF | View/Open | |
12_chapter-1.pdf | 336.37 kB | Adobe PDF | View/Open | |
13_chapter-2.pdf | 630.12 kB | Adobe PDF | View/Open | |
14_chapter-3.pdf | 1.71 MB | Adobe PDF | View/Open | |
15_chapter-4.pdf | 965.53 kB | Adobe PDF | View/Open | |
16_chapter-5.pdf | 791.23 kB | Adobe PDF | View/Open | |
17_chapter-6.pdf | 3.74 MB | Adobe PDF | View/Open | |
18_chapter-7.pdf | 162.64 kB | Adobe PDF | View/Open | |
19_appendix.pdf | 356.74 kB | Adobe PDF | View/Open |
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