1. Shodhganga@INFLIBNET
  2. Aligarh Muslim University
  3. Department of Electronics Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/63568
Title: Low power techniques and architectures FDR field prdgrammable gate arrays
Researcher: Kadir, Kureshi Abdul
Guide(s): Hasan, Mohd
Keywords: Motivation, Contribution, Sources of Power Consumption, CMOS Circuits, Short-Circuit Power, Dual Power Supply, Adaptive Body Bias
University: Aligarh Muslim University
Completed Date: 2010
Abstract: Abstract available newline newline
Pagination: xviii, 170p.
URI: http://hdl.handle.net/10603/63568
Appears in Departments:Department of Electronics Engineering

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01_title.pdfAttached File347.33 kBAdobe PDFView/Open
02_abstract.pdf581.6 kBAdobe PDFView/Open
03_certificate.pdf31.82 kBAdobe PDFView/Open
04_acknowledgement.pdf34.58 kBAdobe PDFView/Open
05_contents.pdf139.21 kBAdobe PDFView/Open
06_tables.pdf42.08 kBAdobe PDFView/Open
07_figures.pdf182.57 kBAdobe PDFView/Open
08_symbols.pdf50.8 kBAdobe PDFView/Open
09_abbreviations.pdf57.83 kBAdobe PDFView/Open
10_chapter 1.pdf304.7 kBAdobe PDFView/Open
11_chapter 2.pdf1.49 MBAdobe PDFView/Open
12_chapter 3.pdf3.62 MBAdobe PDFView/Open
13_chapter 4.pdf1.31 MBAdobe PDFView/Open
14_chapter 5.pdf5.92 MBAdobe PDFView/Open
15_chapter 6.pdf495.06 kBAdobe PDFView/Open
16_chapter 7.pdf3.27 MBAdobe PDFView/Open
17_chapter 8.pdf4.41 MBAdobe PDFView/Open
18_chapter 9.pdf1.09 MBAdobe PDFView/Open
19_chapter 10.pdf660.63 kBAdobe PDFView/Open
20_appendix.pdf179.07 kBAdobe PDFView/Open
21_references.pdf872.58 kBAdobe PDFView/Open
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