1. Shodhganga@INFLIBNET
  2. Cochin University of Science & Technology
  3. Department of Computer Science
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/6244
Title: An error localization validation and optimization tool for embedded code augmentation an architecture oriented approach
Researcher: Chacko, Mariamma
Guide(s): Jacob, K Poulose
Keywords: Computer Sciences
Programmable System on Chip
Embedded System
Fault Localization Techniques
Upload Date: 9-Jan-2013
University: Cochin University of Science and Technology
Completed Date: 22/08/2011
Abstract: Included
Pagination: xxiii, 182p.
URI: http://hdl.handle.net/10603/6244
Appears in Departments:Department of Computer Science

Files in This Item:
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01_title.pdfAttached File187.52 kBAdobe PDFView/Open
02_certificate & declaration.pdf92.81 kBAdobe PDFView/Open
03_acknowledgements.pdf52.27 kBAdobe PDFView/Open
04_abstract.pdf99.19 kBAdobe PDFView/Open
05_contents.pdf161.18 kBAdobe PDFView/Open
06_list of tables figures abbreviations.pdf129.68 kBAdobe PDFView/Open
07_chapter 1.pdf222.51 kBAdobe PDFView/Open
08_chapter 2.pdf496.25 kBAdobe PDFView/Open
09_chapter 3.pdf170.52 kBAdobe PDFView/Open
10_chapter 4.pdf615.83 kBAdobe PDFView/Open
11_chapter 5.pdf700.67 kBAdobe PDFView/Open
12_chapter 6.pdf151.22 kBAdobe PDFView/Open
13_appendix.pdf201.91 kBAdobe PDFView/Open
14_references.pdf233.86 kBAdobe PDFView/Open
15_list of publications & index.pdf3.32 MBAdobe PDFView/Open
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