Architectural Design of Router for Network on Chip

Abstract

Multi-core processors connect thousands of cores using NoC, in place of shared buses or pointto- newlinepoint connection wires. It has the fundamental building pieces, including routing, topology,and flow control. Traditionally employed IQR places packets in each VC in a specific order. newlineDue to the switch allocator s limited ability to allocate packets, this approach is susceptible to newlineHoL blocking. By improvising on architectural challenges and overcoming design constraints, newlinethe objective of this work is to decrease average packet delay, reduce wire overhead, and boost NoC routers allocation services.Initially, the SB registers are used for scheduling the packets stored in input buffers, facilitating the design of SB-Router architecture. The VCs are built as SBs, so as to enable SA newlinefor both the VC head packet and the packets kept in the SB registers. In our work, a VC newlineallocation mechanism is created to help with the input buffer s packet order. Additionally, Fill newlineVC allocation is integrated with SB-Router. For uniform traffic with an injection rate of 0.42 flits/cycle, SB-Router-1, having one SB register exhibits a 68.75 percent drop in latency when newlinecompared to the baseline router.Later, the currently existing SMART NoC is modified, and the Turn-to-west-first technique newlineis utilized to create express bypass channels where all bypass requests are sent simultaneously newlinewith flits. The router design has incorporated the methods such as adaptive routing, combined newlinewormhole switching and virtual cut-through. In our work, the wire overhead is calculated newlineusing mathematical modeling. Based on these factors, a novel router architecture is created newlineto enable the flits to travel both one and two-dimensional pathways without latching in any newlinebypass router. The launch latency and wire overhead for SMART NoC is reduced by NoC newlineusing express bypass channels.To improve NoC routers allocation, a new pipeline stage called RF is added before the newlineSA stage. The RF stage s objective is to complete the uniform request and EPC requests ...