Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/598223
Title: VLSI design and hardware acceleration of speech coding algorithms using FPGA
Researcher: Singh, Dilip
Guide(s): Chandel, Rajeevan
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: National Institute of Technology Hamirpur
Completed Date: 2024
Abstract: newline
Pagination: xxviii, 173
URI: http://hdl.handle.net/10603/598223
Appears in Departments:Department of Electronics and Communication Engineering

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01_title.pdfAttached File155.34 kBAdobe PDFView/Open
02_prelim pages.pdf763.54 kBAdobe PDFView/Open
03_content.pdf147.86 kBAdobe PDFView/Open
04_abstract.pdf133.31 kBAdobe PDFView/Open
05_chapter 1.pdf379.34 kBAdobe PDFView/Open
06_chapter 2.pdf442.36 kBAdobe PDFView/Open
07_chapter 3.pdf898.36 kBAdobe PDFView/Open
08_chapter 4.pdf1.32 MBAdobe PDFView/Open
09_chapter 5.pdf654.91 kBAdobe PDFView/Open
10_chapter 6.pdf220.51 kBAdobe PDFView/Open
11_annexures.pdf307.16 kBAdobe PDFView/Open
80_recommendation.pdf367.98 kBAdobe PDFView/Open
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