Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/598223
Title: | VLSI design and hardware acceleration of speech coding algorithms using FPGA |
Researcher: | Singh, Dilip |
Guide(s): | Chandel, Rajeevan |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | National Institute of Technology Hamirpur |
Completed Date: | 2024 |
Abstract: | newline |
Pagination: | xxviii, 173 |
URI: | http://hdl.handle.net/10603/598223 |
Appears in Departments: | Department of Electronics and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 155.34 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 763.54 kB | Adobe PDF | View/Open | |
03_content.pdf | 147.86 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 133.31 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 379.34 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 442.36 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 898.36 kB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 1.32 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 654.91 kB | Adobe PDF | View/Open | |
10_chapter 6.pdf | 220.51 kB | Adobe PDF | View/Open | |
11_annexures.pdf | 307.16 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 367.98 kB | Adobe PDF | View/Open |
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