An Efficient and Lightweight Authentication Architecture using a Hash based Post Quantum Signature Scheme for Industry 4 0

Abstract

In today s era, Smart applications are rapidly evolving through technologies like IoT, AI, and Big Data. Advanced sensors, AI-driven devices, and cloud-based control have greatly improved IoT application efficiency and profitability. In Industry 4.0, secure authentication is crucial to prevent unauthorized activities and hazardous situations. Current cryptographic methods in IoT devices, based on public-key cryptographic primitives, are vulnerable to future quantum attacks using Shor s and Grover s algorithms. newlineGiven the low processing capabilities of IoT devices, there is a pressing need for an effective, lightweight signature scheme that ensures secure authentication against quantum threats in Industry 4.0. newlineResearch in post-quantum cryptography PQC aims to develop algorithms resistant to attacks from both classical and quantum computers, based on mathematical problems difficult for quantum computers. Hash-based cryptography is a promising candidate for quantum-resistant authentication, offering smaller key and signature sizes, making it suitable for Industry 4.0 and IoT. However, hash-based schemes, involving complex tree structures and intensive mathematical operations, can be challenging to implement efficiently on IoT devices with limited computational resources. Through theoretical newlineand practical implementations, it has been observed that eXtended Mekle Signature Scheme XMSS with Optimized Winternitz One-Time Signature scheme WOTS+ performs key generation, signature generation, and verification faster than Merkle Signature Scheme MSS variants. This study demonstrates a practical client-server implementation for Industry 4.0 using hash-based post-quantum digital signatures. The key generation process takes up 98% of the authentication time, posing a challenge for constrained devices like microcontrollers. A client-server authentication architecture is proposed to reduce the computational burden on microcontroller devices, enabling faster performance. newline newline