1. Shodhganga@INFLIBNET
  2. Vellore Institute of Technology, Vellore
  3. School of Electronic Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/594798
Title: Enhanced DFT Methodologies for Improvement In Test Coverage And Yield In Finfet Circuits
Researcher: Renold Sam Vethamuthu .E
Guide(s): Sivanantham S
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Vellore Institute of Technology, Vellore
Completed Date: 2024
Abstract: newline
Pagination: 1-128
URI: http://hdl.handle.net/10603/594798
Appears in Departments:School of Electronic Engineering

Files in This Item:
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01_title.pdfAttached File65.26 kBAdobe PDFView/Open
02_preliminary pages.pdf4.91 MBAdobe PDFView/Open
03_table_of_content.pdf47.27 kBAdobe PDFView/Open
04_abstract.pdf58.03 kBAdobe PDFView/Open
05_chapter_1.pdf275.21 kBAdobe PDFView/Open
06_chapter2.pdf830.77 kBAdobe PDFView/Open
07_chapter_3.pdf1.24 MBAdobe PDFView/Open
08_chapter_4.pdf2.66 MBAdobe PDFView/Open
09_chapter_5.pdf1.32 MBAdobe PDFView/Open
10_chapter_6.pdf46.86 kBAdobe PDFView/Open
11_annexures.pdf156.5 kBAdobe PDFView/Open
80_recommendation.pdf114.58 kBAdobe PDFView/Open
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