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http://hdl.handle.net/10603/594472
Title: | 3D Graphics of Digital Multiplier and Deep Neural Learning based Deming Regression adder Enhancement for Efficient VLSI Design |
Researcher: | MANNE RENUKA |
Guide(s): | MARY VALANTINA G |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Sathyabama Institute of Science and Technology |
Completed Date: | 2023 |
Abstract: | In domain of VLSI industry, minimum power, time, as well as area-effective designs are often desired for different applications. Adders as well as multipliers play a fundamental task in VLSI circuit designs. Among various multiplier design, VLSI system with adder gives optimized system performance. Enhanced performance VLSI adders vital basics in widespread use as well as digital-signal processing processors as applied in design of Arithmetic-Logic Units, in floating-point arithmetic data paths and so on. Needs of adder are quick and effective during power consumption, area. Parallel Prefix adders are generally applied in computerized plan. Besides, many graphical applications with digital multiplier have been designed by several researchers to determine the adder enhancement. The design of three-dimensional integrated circuit was not improved in terms of minimal time and area and power requirement. To improve VLSI design by using adder enhancement, novel methods are proposed in this research. newlineIn first research work, Novel Dual-Channel Multiplier (NDCM) approach is designed for carry outing adder enhancement of digital multiplier in VLSI design. NDCM includes three main parts such as data preprocessing, carry generation and post processing process. In preprocessing, unnecessary signals are eliminated and preprocessed carry data is attained with list of adders. Next, carry generation process is performed to carry single bit of data at the operation using two gates such as AND gate OR gate. With generated carry bit, post processing is performed using to improve the adder enhancement with less time. newlineix newlineDeep Fully Connectedness Convolutional Broken Stick Regressive Brent Kung Adder Enhancement (DFCCBSRBKAE) method is designed during second research work for efficient VLSI design. DFCCBSRBKAE is designed with the objective of reducing area, delay of VLSI circuits design. This can be done by using input layer, hidden layers as well as output layer. Input layer obtains information from digital signal processing. |
Pagination: | vi, 162 |
URI: | http://hdl.handle.net/10603/594472 |
Appears in Departments: | ELECTRONICS DEPARTMENT |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | Attached File | 135.91 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 701.92 kB | Adobe PDF | View/Open | |
03_content.pdf | 261.45 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 95.8 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 226.16 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 165.03 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 667.57 kB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 502.44 kB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 786.96 kB | Adobe PDF | View/Open | |
10_chapter 6.pdf | 321.32 kB | Adobe PDF | View/Open | |
11_chapter 7.pdf | 41.9 kB | Adobe PDF | View/Open | |
12_annexures.pdf | 3.99 MB | Adobe PDF | View/Open | |
80_recommendation.pdf | 135.91 kB | Adobe PDF | View/Open |
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