Investigations on digital filter using proficient vlsi arithmetic architecture in signal processing applications

Abstract

The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response (FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. The speed of electronic devices depends on arithmetic operations. Multiplication is the important arithmetic operation in many VLSI signal processing applications. One of the architectures used in the high-speed addition operation is carry select adder. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on the partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. newline