Design and Analysis of Software Defined Radio Transmitter for 5G Applications

Abstract

This thesis presents an efficient embedded computing architecture for the MIMO-OFDM and MIMO-OFDM-DBF system, featuring both programmability and reconfigurability for improved throughput. The developed embedded architecture is reconfigurable to perform as MIMO or MIMO-DBF or OFDM or OFDMA or MIMO-OFDM or MIMO-OFDM-DBF systems through programmable in hardware and software co-design. Simulation models serving as software architecture are developed for MIMO, MIMO-DBF, OFDM, OFDMA, MB-OFDMA, MIMO-OFDM and MIMO-OFDM-DBF systems to estimate their BER and throughput performance. Simulation studies carried out on the implementation of the developed software reference models on embedded architecture configured with the advanced processors of ARM families, reveal their inadequacy to meet the data rate requirements of 4G and 5G applications. Given the challenges of meeting the enormity of throughput and data rate requirements of emerging systems applications like 5G, this thesis proposes to modify the design of the computing architectures of MIMO, OFDM, MIMO-OFDM and MIMO-OFDM-DBF systems to increase their throughput. This thesis analyses the application of Systolic and CORDIC architectures to arrive at new design configurations of MIMO and OFDM systems. Systolic architecture is applied to develop the Viterbi Decoder, a sub system of MIMO. CORDIC architecture is applied in the development of programmable QAM to enhance the throughput and data rate of both MIMO and OFDM systems. Since OFDM is an extensively used modulation technique for the significant improvement of data rate, this thesis also focuses on the optimisation of the performance of FFT/IFFT blocks. This thesis proposes partitioning the OFDM system design to make simultaneous use of CPU-GPU and FPGA with the execution of FFT/IFFT blocks on GPU and Programmable QAM on FPGA. Other sub blocks of OFDM, such as the Viterbi decoder and programmable QAM, are chosen for their implementation on FPGA using Systolic and CORDIC architectures. The simulation results in baseband reveal that the developed programmable embedded architecture for MIMO and MIMO-DBF systems. newline