Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/589906
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dc.coverage.spatial
dc.date.accessioned2024-09-18T06:30:17Z-
dc.date.available2024-09-18T06:30:17Z-
dc.identifier.urihttp://hdl.handle.net/10603/589906-
dc.description.abstractAttached
dc.format.extent176pp.
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleLeakage Current Utilization approach in Subthreshold Logic for SOC Design
dc.title.alternative
dc.creator.researcherAchutha Jyotsna Koppaka
dc.subject.keywordCMOS Logic
dc.subject.keywordCurrent Mode Logic (CML)
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordSARADC
dc.subject.keywordSubthreshold Source Coupled Logic
dc.subject.keywordVCOADC
dc.description.note
dc.contributor.guideSatish Kumar P and Madhavi B K
dc.publisher.placeKukatpally
dc.publisher.universityJawaharlal Nehru Technological University, Hyderabad
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2012
dc.date.completed2024
dc.date.awarded2024
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
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01_title.pdfAttached File90.63 kBAdobe PDFView/Open
02_prelim pages.pdf688.08 kBAdobe PDFView/Open
03_contents.pdf103.65 kBAdobe PDFView/Open
04_abstract.pdf52.4 kBAdobe PDFView/Open
05_chapter 1.pdf293.64 kBAdobe PDFView/Open
06_chapter 2.pdf435.02 kBAdobe PDFView/Open
07_chapter 3.pdf388.97 kBAdobe PDFView/Open
08_chapter 4.pdf546.91 kBAdobe PDFView/Open
09_chapter 5.pdf246.92 kBAdobe PDFView/Open
10_chapter 6.pdf239.53 kBAdobe PDFView/Open
11_chapter 7.pdf265.67 kBAdobe PDFView/Open
12_chapter 8.pdf70.51 kBAdobe PDFView/Open
13_annexures.pdf195.06 kBAdobe PDFView/Open
80_recommendation.pdf148.81 kBAdobe PDFView/Open


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