An Analylitical Characterization Of Ultra Thin Film Surrounding Gate Mosfet For High Density Memory Application

Abstract

newline The scaling of conventional MOSFET has been the most prominent technological newlinechallenge in the past few years. In order to acquire high speed and packing density, newlinethe dimension of MOSFET has been shrinking depending on the scaling law. But as newlinethe device dimensions are decreased, the sharing of charges from the source to drain newlineincreases which results in reduction of gate control over the channel depletion region. newlineThus, decrease in the channel length of the device leads to short channel effects newline(SCEs) such as drain induced barrier lowering (DIBL), threshold voltage roll off (Vth), newlinepunch through, channel length modulation (CLM) and hot carrier effects (HCEs). newlineReduction in channel width also leads to a reduction in the current drivability and hot newlinecarrier induced degradation due to large electric field at the field isolation edge. These newlineunfavorable effects devaluate the device performance. To surmount the scaling newlinelimitations of planar MOSFETs, many devices are designed through innovative newlinedevice design/architecture. High quality materials are used for nanoscale applications. newlineThese includes multiple gate structures such as double gate (DG), triple gate or fin newlineshaped gate (FinFET), surrounded/cylindrical gate (SGT/CGT) or gate all round gate newline(GAA) MOSFET. These structures have better gate controllability over the channel newlineregion; hence can be adapted for manufacturing integrated circuits (IC). These newlinestructures offer higher drive current, low subthreshold slope, and high packing newlinedensities than their conventional counterpart. These factors lead to strong newlineenhancement of the immunity toward the short channel effects (SCEs). Out of these newlinecylindrical/surrounded gate MOSFET (CGT/SGT MOSFET) is one of the most newlinepromising solutions for controlling the scaling limitations and increasing the device newlineperformance. In SG MOSFET structure, the source, drain and gate are arranged newlinevertically and the sidewalls of the pillar are used as the channel region. Since the newlinesidewalls of the silicon pillar can be used as channel region,