Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/581668
Title: | Development of ASIC based computational unit for stand alone image processing applications |
Researcher: | Mendez, Tanya |
Guide(s): | Nayak, Subramanya G |
Keywords: | Application Specific Integrated Circuit, Discrete cosine transform error-tolerant adder, fixed-point multiplier, low-power pipelining, Verilog, power delay product, PSNR |
University: | Manipal Academy of Higher Education |
Completed Date: | 2024 |
Abstract: | Available newline |
Pagination: | 142p. |
URI: | http://hdl.handle.net/10603/581668 |
Appears in Departments: | Manipal Institute of Technology |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 273.45 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 689.2 kB | Adobe PDF | View/Open | |
03_content.pdf | 47.15 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 48.06 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 3.21 MB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 563.6 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 5.63 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 8.09 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 23.62 MB | Adobe PDF | View/Open | |
10_annexures.pdf | 132.76 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 341.8 kB | Adobe PDF | View/Open |
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