A PVT aware Surrogate Modeling Framework for Digital Analog and Mixed Signal VLSI Circuits

Abstract

The invention of Complementary Metal Oxide Semiconductor (CMOS) transistors marked a revolutionary newlineshift in the field of electronics, ushering in the era of semiconductor devices within the newlineIntegrated Circuit (IC) industry. Since then, CMOS technology has dominated the realm of microelectronics. newlineThe key to advancing ICs lies in transistor scaling, which boosts transistor density, switching newlinespeed, and operational frequency, enabling the creation of higher-performing electronic circuits. However, newlinethe aggressive down-scaling of CMOS technology has posed challenges for device engineers while newlineopening up new opportunities. As transistor dimensions decrease, the complexity of the semiconductor newlineprocess increases. As we approach atomic scales, simple scaling reaches its limits. Despite their minute newlinesize, devices can encounter various performance issues, including increased leakage, reduced gain, and newlineincreased sensitivity to manufacturing process variations. The substantial rise in process variations significantly newlineimpacts circuit operation, resulting in variable performance even in transistors of identical newlinesize. This, in turn, affects the propagation delay of the circuit, which behaves as a stochastic random newlinevariable, making timing-closure techniques more complex and exerting a substantial influence on chip newlineyield. FinFETs, which have superseded CMOS in the nanoscale IC designs, also face performance newlinedeviations due to process variations despite demonstrating good resistance to Short Channel Effects newline(SCE). Surging process variations in the nanometer regime significantly contribute to the degradation of newlineparametric yield. newlineUnder such scenarios, the Process, Voltage, and Temperature (PVT) aware performance estimation newlineof VLSI circuits through traditional Electronic Computer Aided Design (E-CAD) tools is a complex endeavor. newlineThese tools often exhibit intricacies, heavily relying on specific circuit architectures and licensing newlineagreements, while demanding significant simulation times proportional to the design complexity. newlineMoreover, c