Modelling of Charge Spin and Valley Transport in Topological Insulators for Design of Hetro Interfaces

Abstract

The electronics fabrication industry is being dominated by a single semiconductor material called Silicon for many decades now. The fabrication of devices is governed by the golden law called Moore s Law which states that the number of transistors on an integrated circuit doubles every two years. This law has led to the reduction in size of the ICs through the ages. Nanotechnology has provided an extension to Moor s Law and helped in further miniaturization of the devices. But this law has now reached its functional limit and with the existing Lithographic techniques further miniaturization of ICs will not be possible. In order to facilitate the ever growing demands and to make pace with the rapid advancements in technology, it is required to develop higher order of advanced materials with modified electronic and spin transport properties for development of next-generation devices and various other applications. newline