Studies on transparent conducting oxides for CdTe solar cell application

Abstract

This thesis describes the studies on TCOs for CdTe solar cell application. Cadmium stannate thin films are prepared by spray pyrolysis technique using a set of new precursors (cadmium acetate and tin (II) chloride). Films prepared at substrate temperature of 450 °C are amorphous and films prepared at 500 °C produce Cd2SnO4 films in (111) hkl orientation in orthorhombic structure with resistivity of 35.6 x 10-4 and#937; cm. A new procedure of cover layer formation has been introduced to improve the electrical property of the film without affecting the optical and structural properties. The minimum resistivity of 6 and#61655;and#61472;10-4 and#937; cm was obtained for the films prepared with cover layer procedure. X-ray Photoelectron Spectroscopy (XPS) was used to study the CdS/ITO and CdS/SnO2/ITO interface properties with the help of XPS sputter depth profile technique. CdS/ITO interface studies show that indium is diffusing through CdS layer when the sample is treated with different heat treatments. But CdS/SnO2/ITO interfaces show that the SnO2 buffer layer acts as a barrier for the indium diffusion from ITO to CdS. Different post annealing treatments (vacuum annealing, air annealing and CdCl2 activation) on CdS/ITO and CdS/SnO2/ITO do not lead to considerable change in band offset in these interfaces. Results from the present study show that the valence band offsets are 1.25 and#61617;and#61472;0.1eV for the CdS/ITO and 1.5 and#61617;and#61472;0.1 eV for CdS/SnO2 interface, respectively. Solar cells prepared using ITO/SnO2 substrates with CdS layer thickness of ~140 nm yields efficiency and#951; = 9.5%. Reducing the CdS film thickness to ~60-70 nm results poor device performance with low efficiency (and#951; = 4.8%) due to the presence of pin holes. A new method of forming CdS double layer has been introduced to reduce the CdS film thickness and to avoid pinholes. In the case of double layer procedure, a thin CdS layer of ~50?60nm was deposited at standard substrate temperature of ~520 °C and the second layer of ~10-20nm was deposited at low substrate temperature of ~250 °C.