1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Delhi
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/558595
Title: Design and analysis of emerging nanoscale junctionless fets from gate induced drain leakage perspective
Researcher: Sahay, Shubham
Guide(s): Kumar, Mamidala Jagadesh
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Delhi
Completed Date: 2018
Abstract: Abstract Available newline newline
Pagination: NA
URI: http://hdl.handle.net/10603/558595
Appears in Departments:Department of Electrical Engineering

Files in This Item:
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01_title.pdfAttached File124.56 kBAdobe PDFView/Open
02_prelim pages.pdf5.98 MBAdobe PDFView/Open
03_content.pdf980.43 kBAdobe PDFView/Open
04_abstract.pdf1.06 MBAdobe PDFView/Open
05_chapter 1.pdf12.23 MBAdobe PDFView/Open
06_chapter 2.pdf8.8 MBAdobe PDFView/Open
07_chapter 3.pdf5.33 MBAdobe PDFView/Open
08_chapter 4.pdf12.35 MBAdobe PDFView/Open
09_chapter 5.pdf6.62 MBAdobe PDFView/Open
10_chapter 6.pdf7.41 MBAdobe PDFView/Open
11_chapter 7.pdf5.03 MBAdobe PDFView/Open
12_chapter 8.pdf4.81 MBAdobe PDFView/Open
13_chapter 9.pdf5.22 MBAdobe PDFView/Open
14_chapter 10.pdf7.71 MBAdobe PDFView/Open
15_chapter 11.pdf4.13 MBAdobe PDFView/Open
16_chapter 12.pdf4.14 MBAdobe PDFView/Open
17_chapter 13.pdf2.62 MBAdobe PDFView/Open
18_annexures.pdf2.44 MBAdobe PDFView/Open
80_recommendation.pdf2.74 MBAdobe PDFView/Open
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