1. Shodhganga@INFLIBNET
  2. Koneru Lakshmaiah Education Foundation
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/555855
Title: 14 Transistor and 12 Transistor Memory Cells for Ultra Low Power Design Using Dual Edge Triggering
Researcher: K Mariya Priyadarsini
Guide(s): Dr. R.S.Ernest Ravindra
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Koneru Lakshmaiah Education Foundation
Completed Date: 2023
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/555855
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File31.09 kBAdobe PDFView/Open
02_declaration.pdf5.28 kBAdobe PDFView/Open
03_certificate.pdf128.19 kBAdobe PDFView/Open
04_acknowledgement.pdf7.77 kBAdobe PDFView/Open
05_abstract.pdf106.38 kBAdobe PDFView/Open
06_table of contents.pdf188.38 kBAdobe PDFView/Open
07_list of figure contents.pdf140.45 kBAdobe PDFView/Open
09_chapter-1.pdf835.21 kBAdobe PDFView/Open
10_chapter-2.pdf1.09 MBAdobe PDFView/Open
11_chapter-3.pdf958.49 kBAdobe PDFView/Open
12_chapter-4.pdf395.98 kBAdobe PDFView/Open
13_chapter-5.pdf620.96 kBAdobe PDFView/Open
14_chapter-6.pdf26.13 kBAdobe PDFView/Open
15_chapter-7.pdf184.69 kBAdobe PDFView/Open
16_list of publications.pdf117.15 kBAdobe PDFView/Open
80_recommendation.pdf4.72 MBAdobe PDFView/Open
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