Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/554262
Title: | Designing cache management techniques for power efficient chip multiprocessors |
Researcher: | Kulkarni, Ashwini Anil |
Guide(s): | Mahajan, S. P. |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Savitribai Phule Pune University |
Completed Date: | 2022 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/554262 |
Appears in Departments: | College of Engineering Pune |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 506.75 kB | Adobe PDF | View/Open |
02_preliminary_pages.pdf | 1.24 MB | Adobe PDF | View/Open | |
03_contents.pdf | 505.24 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 689.44 kB | Adobe PDF | View/Open | |
05_chapter1.pdf | 1.49 MB | Adobe PDF | View/Open | |
06_chapter2.pdf | 952.49 kB | Adobe PDF | View/Open | |
07_chapter3.pdf | 1.23 MB | Adobe PDF | View/Open | |
08_chapter4.pdf | 1.17 MB | Adobe PDF | View/Open | |
09_chapter5.pdf | 2.99 MB | Adobe PDF | View/Open | |
10_chapter6.pdf | 827.55 kB | Adobe PDF | View/Open | |
11_annexures.pdf | 1.32 MB | Adobe PDF | View/Open | |
80_recommendation.pdf | 909.94 kB | Adobe PDF | View/Open |
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