Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/554262
Title: Designing cache management techniques for power efficient chip multiprocessors
Researcher: Kulkarni, Ashwini Anil
Guide(s): Mahajan, S. P.
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Savitribai Phule Pune University
Completed Date: 2022
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/554262
Appears in Departments:College of Engineering Pune

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01_title.pdfAttached File506.75 kBAdobe PDFView/Open
02_preliminary_pages.pdf1.24 MBAdobe PDFView/Open
03_contents.pdf505.24 kBAdobe PDFView/Open
04_abstract.pdf689.44 kBAdobe PDFView/Open
05_chapter1.pdf1.49 MBAdobe PDFView/Open
06_chapter2.pdf952.49 kBAdobe PDFView/Open
07_chapter3.pdf1.23 MBAdobe PDFView/Open
08_chapter4.pdf1.17 MBAdobe PDFView/Open
09_chapter5.pdf2.99 MBAdobe PDFView/Open
10_chapter6.pdf827.55 kBAdobe PDFView/Open
11_annexures.pdf1.32 MBAdobe PDFView/Open
80_recommendation.pdf909.94 kBAdobe PDFView/Open
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