Delay Modeling of Inductance Dominated VLSI Interconnects

Abstract

As VLSI circuits move into the era of deep sub-micron (DSM) technologies and newlinegigahertz frequencies, the system performance is increasingly becoming dominated newlineby the interconnect delay. While several delay models exist in literature, they are, newlineby and large, applicable to technologies at and above 130nm. Thus there is a need newlineto evolve techniques that can estimate the interconnect delay with a reasonable newlineaccuracy in DSM technologies such as 90nm. newlineThe objectives of this thesis are three fold. (i) To develop a novel model order newlinereduction (MOR) to reduce the complexity of large integrated circuits and therefore newlinesimplify the estimation of signal delay in interconnects and (ii) To develop novel newlineanalytical and statistical techniques for delay modeling of inductance-dominated newline(RLC) interconnects. newlineThe first contribution of the thesis is the development of a novel MOR technique newlineto reduce the complexity of large integrated circuits. The purpose of any MOR newlinetechnique is to replace a model by its approximation, which, while simplifying newlinethe analysis, also preserves essential properties like stability and passivity of the newlineoriginal model within a certain accuracy. The MOR technique proposed in this newlinethesis satisfies these conditions and an analysis of the technique indicates that it newlineperforms better than any of the existing techniques. newlineOnce the reduced model of large circuit is derived, then analytical or statistical newlinetechniques can be applied to estimate the signal delay in interconnect. The second newlinecontribution of the thesis is the development of an Erlang distribution-based newlinestatistical technique to estimate the delay in inductance-dominated interconnects. newlineIt is shown that this technique performs better than other similar techniques for newlineestimation of delay. newlineThe third and final contribution of the thesis is the development of a novel newlineanalytical delay model based on difference model approach. The model has been newlineapplied to an interconnect tree with various combinations of source and load newlineparameters under step input excitation. It is fou