Simulation and synthesis of soft error correction techniques for SRAM memory

Abstract

The major goal of this research is to design soft error hardened circuit that can avoid, detect and rectify soft errors for high speed memory applications at the same timing phase. The proposed cell designs use nanoscale technology newlinefor checking different particle strikes along with the process, voltage, temperature variation impacts and also by means of some parametric analysis. newlineAvoidance and detection-correction parts can fully bear the single or multiple event particles striking in any of the internal nodes. All types of particle strikes can be detected with this proposed cell design I. According to the performance study, the proposed methods when compared to the existing methodologies, achieves better power consumption and lower delay overheads due to the avoidance and detection-correction parts. But transient pulses of particular particle strikes cannot be filtered. Transient pulses are being completely filtered by the filtering part along with the avoidance and detection correction parts of the proposed cell design II. The transient pulses that occur along with the input are fully filtered before they reach either the output node or the storage node. The event strikes upsetting the nodes are corrected by the detection-correction part after detecting the occurrence of error at that particular node. But this requires extra overheads than the previous cell design I. The cross-coupled inverter has nodes when designed using a CMOS structure for storing the collected information called storage nodes. There are several possibilities for these nodes to get stuck by any faults. The drain area of PMOS or NMOS mainly gets stuck during particle strike faults. This causes the flipping of stored data. newline newline