Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/545307
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dc.coverage.spatial
dc.date.accessioned2024-02-14T08:44:02Z-
dc.date.available2024-02-14T08:44:02Z-
dc.identifier.urihttp://hdl.handle.net/10603/545307-
dc.description.abstractFile attached newline
dc.format.extentxiii, 458p
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titlePerformance enhancement in DRAM using leakage reduction technique
dc.title.alternative
dc.creator.researcherSankpal, Amol Shashikant
dc.subject.keywordDRAM cell
dc.subject.keywordDynamic Random Access Memory (DRAM)
dc.subject.keywordElectronics Engineering
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordLeakage parameter analysis
dc.subject.keywordLeakage parameter reduction techniques
dc.description.noteLocation - Knowledge Resource Centre, Kalina
dc.contributor.guidePete, Dnyandeo J
dc.publisher.placeMumbai
dc.publisher.universityUniversity of Mumbai
dc.publisher.institutionElectronics Engineering, Datta Meghe College of Engineering
dc.date.registered2019
dc.date.completed2022
dc.date.awarded2023
dc.format.dimensions30*21
dc.format.accompanyingmaterialCD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics Engineering, Datta Meghe College of Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File44.93 kBAdobe PDFView/Open
02_prelim pages.pdf2.47 MBAdobe PDFView/Open
03_contents.pdf290.5 kBAdobe PDFView/Open
04_abstract.pdf5.74 kBAdobe PDFView/Open
05_chapter 1.pdf237.57 kBAdobe PDFView/Open
06_chapter 2.pdf201.94 kBAdobe PDFView/Open
07_chapter 3.pdf145.23 kBAdobe PDFView/Open
08_chapter 4.pdf394.23 kBAdobe PDFView/Open
09_chapter 5.pdf526.42 kBAdobe PDFView/Open
10_chapter 6.pdf708.17 kBAdobe PDFView/Open
11_chapter 7.pdf9.44 kBAdobe PDFView/Open
12_annexures.pdf2.32 MBAdobe PDFView/Open
80_recommendation.pdf53.34 kBAdobe PDFView/Open


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