Design and Simulation of low leakage Quad Gate Stacked Nano Sheets Finfet Device for Application in Memory and Analog Circuits

Abstract

The objective of this PhD work is Design and Simulation of Low Leakage Quad Gate Stacked Nano-Sheets FinFET Device for Application in Memory and Analog Circuits. The need for battery driven equipment is increasing each day like in sensors, wireless gadgets, cell phones and medical implants. It is required that these equipment consume less power during their operation to enhance the battery life. Hence to address this problem, there is a requirement for such a device that can handle the co-existence of low voltage and low power handling capacity. The work in this thesis has been carried out to suggest solutions to these challenges by proposing and implementing a novel device for both analog and digital applications .In this work, a low power and high performance 3D Quad Gate Stacked Nano-sheets FinFET (QG-SNS) device has been designed by adding an additional fourth gate to a tri-gate device and it has been modified to make fins as vertically stacked Nano-sheets. The prerequisite is that the physical parameters must have been calibrated. The designed device has been calibrated and optimized at 30 nm technology node on COGENDA Visual TCAD tool and Visual Fab tool. Simulations have been performed for VGS varying from 0 Volt to 1 Volt. The voltage at drain terminal is kept at 0.05 Volt and 1 Volt for linear and saturation modes respectively. newline To determine the behavior of the semiconductor devices, different physical models have been used in the device design code. The physical models used are basic model, band model, mobility model, Drift Diffusion Model (DDM), and Shockley-Read-hall (SRH) model. The thesis further highlights the different device parameters that have been opted for the design of the proposed device. The impact of the variations in the number of Nano-sheets, work function, source and drain doping concentration on the performance of the device has been analyzed to identify the optimum parameter values to attain an outstanding performance with reference to Subthreshold Slope (SS), OFF current (IOFF) an