Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/544092
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dc.date.accessioned2024-02-06T08:49:42Z-
dc.date.available2024-02-06T08:49:42Z-
dc.identifier.urihttp://hdl.handle.net/10603/544092-
dc.description.abstractnewlineThe thesis deals with the design and development of efficient hardware architectures for the real time computation of a few signal processing algorithms. Mainly this thesis focuses on the low cost and high speed hardware architecture design for the empirical mode decomposition (EMD), ensemble empirical mode decomposition (EEMD), And fast Fourier transform (FFT) algorithm. newline newline-
dc.languageEnglish-
dc.rightsself-
dc.titleEfficient hardware realizations of empirical mode decomposition and some other related algorithms for signal processing in real time-
dc.creator.researcherDas, Kaushik-
dc.subject.keywordEngineering and Technology-
dc.subject.keywordEngineering-
dc.subject.keywordEngineering Electrical and Electronic-
dc.contributor.guidePradhan, Sambhu Nath-
dc.publisher.placeAgartala-
dc.publisher.universityNational Institute of Technology Agartala-
dc.publisher.institutionDepartment of Electronics and Communication Engineering-
dc.date.registered2017-
dc.date.completed2023-
dc.date.awarded2023-
dc.format.accompanyingmaterialDVD-
dc.source.universityUniversity-
dc.type.degreePh.D.-
Appears in Departments:Department of Electronics and Communication Engineering

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01_title.pdf168.65 kBAdobe PDFView/Open
02_prelim pages.pdfAttached File4.76 MBAdobe PDFView/Open
03_content.pdf1.08 MBAdobe PDFView/Open
04_abstract.pdf2.41 MBAdobe PDFView/Open
05_chapter 1.pdf14.02 MBAdobe PDFView/Open
06_chapter 2.pdf10.5 MBAdobe PDFView/Open
07_chapter 3.pdf16.69 MBAdobe PDFView/Open
08_chapter 4.pdf14.61 MBAdobe PDFView/Open
09_chapter 5.pdf11.79 MBAdobe PDFView/Open    Request a copy
10_chapter 6.pdf1.18 MBAdobe PDFView/Open
11_annexures.pdf982.27 kBAdobe PDFView/Open
80_recommendation.pdf1.35 MBAdobe PDFView/Open


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