Theory and Application of Cellular Automata for CMPs Cache System Design

Abstract

Advancement of Very Large Scale Integration (VLSI) technology covers a large area of electronic design automation to support emerging areas of system level designs e.g. processor chip designs. It impacts to our knowledge society as well as to common people, as in every sphere of life the use of computer technology is inevitable. VLSI technology enables chip designers to embed electronic circuits and systems within a chip to achieve increased functionality, miniaturization, performance beneand#64257;ts in terms of increased throughput, speed up, quality of service etc. To achieve the required functionalities of latency sensitive or throughput sensitive applications like cloud severs, data centers, modern complex computing systems etc, superscalar or superpipelined single core CPUs are almost replaced by multicore and manycore processors, more speciand#64257;cally, by Chip Multi processors (CMPs). A large size multi-layer on-chip cache (L1-L4) is required to be and#64257;t into modern processor chips to meet the demand of homogeneous and/or heterogeneous cores. This is to overcome the limitations of simple or hybrid oand#64256;-chip interconnect and memory bandwidth. Traditional SRAM and DRAM could not oand#64256;er required scalability, area shrinkage, speed up, reduced power consumption as demanded in CMPs. So, to implant a large cache within a processor chip, emerging non-volatile memory technology (eNVM) is in place. Though it can oand#64256;er higher package density, area shrinkage, scalability, low leakage power and non-volatility, but still it is limited in CMPs applications. Limited cell endurance and cell lifetime variability is observed within a threshold write counts in eNVM. In addition, repetitive write causes stuck-at fault in eNVM that leads to unreliable memory operation. These factors play signiand#64257;cant role to hinder adoption of large scale eNVM in CMPs. Further, permanent faulty cells may limit chip lifetime at premature stage. newline newline This thesis aims at to study the causes of unreliable operation of on-chip cache in CMPs. The impact of on-chip cache per