Investigation and improvement of performance parameters in a Charge Pump Phase locked loop for 5G applications

Abstract

In communication systems, Phase Locked Loops (PLLs) play a vital role in achiev- newlineing stable and accurate frequency synthesis and modulation. PLLs are commonly em- newlineployed for clock generation, carrier recovery, and frequency synthesis in various com- newlinemunication technologies such as wireless communication systems, digital communi- newlinecation devices, and telecommunication networks. They provide precise frequency and newlinephase synchronization, enabling reliable and efficient transmission of signals. PLLs newlinein communication systems contribute to improved signal quality, reduced interference, newlineand enhanced overall system performance, making them indispensable components in newlinemodern communication technologies. The fundamental goal of this research is to inves- newlinetigate and improve the performance parameters of CP-PLL. The current work takes on newlinethe tough task of achieving these performance parameters simultaneously in a PLL. This newlineresearch conducts a thorough examination of the performance-linked PLL components newlineas well as their design issues. newlineThe VCO is a critical component in many electronic systems, especially in appli- newlinecations such as PLLs and frequency synthesis. The VCO s primary function is to gen- newlineerate an output signal whose frequency can be adjusted based on a control voltage. newlineThe VCO s output frequency directly influences the performance of various systems, including communication systems, wireless transceivers, and signal processing appli- cations. The performance of CSVCO operating at 5 GHz in order to investigate how the device performs with different technology nodes while preserving the same circuit.This study shows the comparative analysis of five stages of CSVCO with an effect on 180nm, 90nm, 45nm, FINFET, CNTFET, and NCFET technologies. The same design newlineis examined with respect to phase noise, power consumption, operating frequency, and newlinefigure of merit.In a CP-PLL, particularly at high frequencies, phase noise, lock range, lock time,and power consumption are becoming the key performance factors. Despite the PLL s s