1. Shodhganga@INFLIBNET
  2. Sant Gadge Baba Amravati University
  3. Department of Engineering and Technology
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/5393
Title: Design and analysis of low power phase locked loop with multiple output using VLSI technology
Researcher: Belorkar, Ujwala A
Guide(s): Ladhake, Siddharth A
Keywords: VLSI technology
Computer Science
Upload Date: 5-Dec-2012
University: Sant Gadge Baba Amravati University
Completed Date: 2010
Abstract: None
Pagination: 153p.
URI: http://hdl.handle.net/10603/5393
Appears in Departments:Department of Engineering and Technology

Files in This Item:
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01_title.pdfAttached File34.65 kBAdobe PDFView/Open
02_certificate.pdf34.62 kBAdobe PDFView/Open
03_declaration.pdf53.06 kBAdobe PDFView/Open
04_acknowledgement.pdf46.82 kBAdobe PDFView/Open
05_contents.pdf6.34 kBAdobe PDFView/Open
06_list of abrivations.pdf24.06 kBAdobe PDFView/Open
07_chapter1.pdf120.17 kBAdobe PDFView/Open
08_chapter2.pdf60.36 kBAdobe PDFView/Open
09_chapter3.pdf162.75 kBAdobe PDFView/Open
10_chapter4.pdf2.68 MBAdobe PDFView/Open
11_chapter5.pdf294 kBAdobe PDFView/Open
12_chapter6.pdf311 kBAdobe PDFView/Open
13_chapter7.pdf322.24 kBAdobe PDFView/Open
14_chapter8.pdf573.68 kBAdobe PDFView/Open
15_chapter9.pdf301.56 kBAdobe PDFView/Open
16_chapter10.pdf245.64 kBAdobe PDFView/Open
17_chapter11.pdf446.5 kBAdobe PDFView/Open
18_conclusion.pdf20.82 kBAdobe PDFView/Open
19_refferences.pdf49.86 kBAdobe PDFView/Open
20_patent.pdf3.77 kBAdobe PDFView/Open
21_annexure.pdf1.16 MBAdobe PDFView/Open
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