Low Power and PVT Variation Tolerant Serializer Design for On Chip Serial Link

Abstract

The dissertation presents a novel mux-latch, latch and inverter logic circuit. These circuits are used to design a low-power 4:1 serializer operating at 8 Gbps in a 0.09-and#956;m CMOS process for high-speed seria IO link. The working principles of individual blocks used in serializer are discussed in detail, as well as analytical models are presented for a better understanding of the power delay trade-off to achieve optimal system performance under PVT variations. Further, the performance of the circuits is studied under the effect of power supply fluctuation due to PDN, and corresponding propagation delay and jitter are analysed for evaluating the robustness of each design. Moreover, the usefulness of these circuits is observed by designing multiple other digital circuits. A 2:1 mux-latch operating at 12.5 Gbps is proposed for a high-speed serial link interface. The same circuit works as a multiplexer and latch simultaneously, using fewer transistor counts and without requiring any additional enable input. The value of delay, average power and FoM are around 35 ps, 257.7 and#956;W, and 65 ns×fJ×and#956;m2, respectively, for a 1.1 V power supply at a 27OC. Due to power supply noise, VP droops and causes the system delay to vary between 35 and 47.2 ps with a noted jitter of 1.4 ns. A new high-frequency latch operating at 20 Gbps for 1.1 V supply voltage is proposed, with corresponding performance parameters of 87.6 ps, 481.4 and#956;W, and 841.2 ns×fJ×and#956;m2, respectively, while driving a load 30 fF. A power-efficient latch with 2-level transistor stacking is presented for lower supply voltage node operation. The design operates with Vdd of0.45 V at 27OC with noted performance parameters of 140.4 ps, 28.5 and#956;W, and 172.6 ns×fJ×µm2, respectively. The VP droops from 0.35 to 0.45 V due to power supply noise, causing the system delay to vary between 140.4 and 352.5 ps with a corresponding jitter of 1.5 ns. Thereafter another low-power latch architecture is designed for a 1.1 V supply voltage at 27OC to obtain an undistorted near-full swing output