Enhancing the Performance of One Dimensional Median Filter in VLSI Architecture

Abstract

In signal and image processing applications, the noise removal is the important step that helps to provide proper information. Median filter is used in many applications, such as handwriting recognition, object segmentation, speech recognition and medical imaging. It is highly effective in eliminating the noise from signal and image. The noises in Electrocardiogram (ECG) and Electroencephalogram (EEG) are removed using various existing architecture as the noise i.e., unwanted signal is combined with the ECG signal while recoding it from the human body and the EEG signal is affected because of intrinsic and extrinsic noise sources. The Intrinsic sources comprises of eyeball motion, cardiac and muscle actions whereas the extrinsic sources comprise of electrode impedance, bad electrode positions, power line interference and dirty hair skin. Therefore, it is required to denoise the ECG and EEG signals to perform the proper diagnosis. Existing architecture has the limitation of more hardware utilization, power consumption, and less frequency. This motivates to consider the median filter for filtering the noise from ECG and EEG signals as its effectiveness in smoothing the spiky noise and preserving the sharp edges in the images. The main objective of this research work is to develop an area and power efficient filter architecture with an effective noise reduction performance. newlineIn this thesis, initially a Low-Cost Carry Look-ahead Adder median filter (LC-CLA- MF) method has been proposed to improve the speed of the median filter architecture. The proposed architecture is evaluated in 8-bit and 16-bit median filter architecture using 180nm technology. Area, power and delay is evaluated for the proposed design in 5 window and 9 window. In FPGA implementation of proposed design, LUT, number of slices, flip flops and frequency is analysed. The analysis shows that the proposed design has low hardware utilization of 45.42%, low power consumption of 2.68% and less delay of 6.65% compared to existing architecture. It s later ex