An energy efficient hybrid DAC based SAR ADC using deep submicron CMOS and large area oxide TFT technologies

Abstract

The successive approximation-register (SAR) analog-to-digital converters (ADCs) have excellent energy efficiency compared to other Nyquist-rate ADCs like Flash,Pipeline, etc. The simplest form of a SAR ADC employs track-and-hold (T/H) switches, a voltage comparator, a digital controller, and a capacitive digital-toanalog converter (DAC). Due to its simple architecture and highly digital and switching intensive behavior, its popularity has been boosted with technology down scaling. However, most of the designs reported in the literature employ binary-weighted capacitive DAC array, whose size increases exponentially with an increase in resolution of the ADC. This exponential increase degrades the conversion speed and energy efficiency of the SAR ADC. One of the best methods to reduce the size of the binary-weighted capacitive DAC array with the increasing resolution is to use two (or more) small-sized sub-DACs to form the complete DAC of the ADC. Though capacitive-resistive hybrid DAC-based SAR ADCs have been reported in the literature, resistive DAC tradeoff between power consumption, active area, and operating speed, which compromise the performance and energy efficiency. On the other hand, limited number of SAR ADCs with capacitive sub-DACs have been reported, which demand calibration logic and additional digital controller circuitry. Charge-Sharing (CS) and Merged-Capacitor Switching (MCS) are the two extensively employed switching schemes in the SAR ADCs. While the CS switching principle works on a single array of binary-weighted capacitive DAC, MCS works on two arrays of binary-weighted capacitive DAC for the differential implementation SAR ADC. It should be noted that though CS DAC employs a single array of capacitive DAC, it requires explicit T/H capacitors to perform the conversion algorithm. In addition, this scheme requires a pre-charging phase, in which the capacitors of the DAC array are charged to the reference voltage. As a result, for moderate to high-resolution ADCs, the DAC size will be significan