Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/534395
Title: Performance Evaluation of Non Volatile Memory for Low Power VLSI Applications
Researcher: Jyoti Garg
Guide(s): Subodh Wairya
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Dr. A.P.J. Abdul Kalam Technical University
Completed Date: 2023
Abstract: The design of electronic logic circuits utilizing spin transfer torque magnetic random memory (STT MRAM), spin hall effect (SHE) assisted STT-MRAM, and memristor is the focus of the research presented in this thesis. A thorough theory about STT-MRAM, SHE, and memristor is presented in the thesis. For a thorough knowledge of the topic, a number of basic concepts and implementations that are available in literature have been discussed. There is a potential for developing novel STT-MRAM and memristor-based logic applications with enhanced circuit parameters including area, circuit complexity, and clock delays. This serves as inspiration for the work done as part of this research program. Additionally, it provides a thorough analysis of non-volatile memory circuits and provides a summary of the current literature in this area. The importance of carrying out study on the subject of this thesis has been convincingly demonstrated. newlineCMOS Technology underpins all the aspects of information generation, storage, transformation, and transmission in the digital age. Moore s law of scaling has aided in the development of information technology even today. Yet we are also getting close to the physical limits of Silicon as we approach the fundamental area, power and performance restrictions of the CMOS. Potential low power substitutes for CMOS technology that would go beyond CMOS are spintronics devices. The most practicable spintronic component that can be employed in the next-generation microprocessor system is thought to be the Magnetic Tunnel Junction (MTJ) based Spin transfer torque Magneto random access Memory (STT-MRAM). In comparison to traditional SRAM-based memory, the STT MRAM has demonstrated various advantages, such as non-volatility, zero static power, and smaller bit cells. Due to its shorter global interconnects, the STT- MRAM is projected to perform better than the SRAM in higher level cache memory applications. Thesis examines the use of these technologies beyond memory in terms of digital and analog application
Pagination: 
URI: http://hdl.handle.net/10603/534395
Appears in Departments:dean PG Studies and Research

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80_recommendation.pdfAttached File23.68 kBAdobe PDFView/Open
abstract.pdf113.29 kBAdobe PDFView/Open
annexure.pdf153.72 kBAdobe PDFView/Open
chapter 1.pdf129.39 kBAdobe PDFView/Open
chapter 2.pdf287.6 kBAdobe PDFView/Open
chapter 3.pdf1.16 MBAdobe PDFView/Open
chapter 4.pdf740.19 kBAdobe PDFView/Open
chapter 5.pdf2.06 MBAdobe PDFView/Open
content.pdf136.47 kBAdobe PDFView/Open
prelim pages.pdf181.71 kBAdobe PDFView/Open
title page.pdf40.45 kBAdobe PDFView/Open
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