Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/534378
Title: | PERFORMANCE INVESTIGATION OF SiGe HETEROJUNCTION GATE STACKED TRIPLE METAL GATE VERTICAL TFET FOR LOW POWER APPLICATION |
Researcher: | SHILPI GUPTA |
Guide(s): | Subodh Wairya |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Dr. A.P.J. Abdul Kalam Technical University |
Completed Date: | 2023 |
Abstract: | The work carried out in this thesis is concerned with the design of electronic logic newlinecircuits The invention of the transistor transformed the electronic industry, and newlinemicroelectronics continues to have a significant impact on all aspects of development. newlineThe spectacular success story of microelectronics, on the other hand, cannot continue newlineindefinitely due to three critical constraints in microelectronics, which include: newlineFundamental Physical Limitations; newlineMaterial Limitations; newlineTechnology Limitations; newlineDevice Limitations and newlineCircuit and System Limitations. newlineAs MOSFET devices are scaled down to nanometer range (Nano-electronics), newlinetransient quantum effects impair their behavior. Alternative fault tolerant technologies are newlineexploited. In the Complementary Metal-Oxide - Semiconductor (CMOS) technology, newlineover the past four decades, scaling has been a gateway to continuous development in the newlinesilicone-based semiconductor industry. However, as the nanometer-sized technology newlinedevelopment framework for the goal of building ultra-high-density integrated electronic newlinecomputers and expanding performance, CMOS devices face fundamental problems such newlineas increased leakage currents, large variations in process parameters, short channel newlineeffects, higher production costs, etc. newlineThe new technology will need to be energy-efficient, dense, and allow more tool newlinefeatures, per unit area and time. There are many nanoscale novels; this thesis discusses newlineand summarizes advances in semiconductor device production of Low Power vertical newlinedesign Tunnel Field-Effect Transistors (TFETs). Owing to its steeper sub-threshold (SS), newlinetunnel FETs are helpful tools for ultra-low power applications having very low OFF newlineiv newlinecurrent. Their operations are based on the controlled switching of quantum-mechanical newlineBand-to-Band Tunneling (BTBT), instead of the thermionic emissions. newlineThis work deals with the novel characterization of n+ SiGe -doped layer with the newlinecombination of gate stacking method in Vertical TFET device by using TCAD simulation newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/534378 |
Appears in Departments: | dean PG Studies and Research |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
80_recommendation.pdf | Attached File | 207.61 kB | Adobe PDF | View/Open |
abstract.pdf | 228.17 kB | Adobe PDF | View/Open | |
annexture.pdf | 772.25 kB | Adobe PDF | View/Open | |
chapter 1.pdf | 1.17 MB | Adobe PDF | View/Open | |
chapter 2.pdf | 403.91 kB | Adobe PDF | View/Open | |
chapter 3.pdf | 957.68 kB | Adobe PDF | View/Open | |
chapter 4.pdf | 1.61 MB | Adobe PDF | View/Open | |
chapter 5.pdf | 689.85 kB | Adobe PDF | View/Open | |
content.pdf | 294.3 kB | Adobe PDF | View/Open | |
prelim page.pdf | 220.11 kB | Adobe PDF | View/Open | |
title page.pdf | 40.23 kB | Adobe PDF | View/Open |
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