Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/532165
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dc.coverage.spatial
dc.date.accessioned2023-12-21T11:32:39Z-
dc.date.available2023-12-21T11:32:39Z-
dc.identifier.urihttp://hdl.handle.net/10603/532165-
dc.description.abstractnewlineNo newline
dc.format.extentx, 246p
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDesign of specific instruction processor using very large scale integration and to study the timing and power analysis of the designed processor
dc.title.alternative
dc.creator.researcherPillai Arun Shridharan Padmavathy
dc.subject.keywordChip Architecture
dc.subject.keywordDebug Module
dc.subject.keywordDesigned Processor
dc.subject.keywordField Programmable Gate Arrays
dc.subject.keywordPerforming Arithmetic
dc.subject.keywordPhysical Sciences
dc.subject.keywordPhysics
dc.subject.keywordPhysics Applied
dc.description.note
dc.contributor.guideDubey, Sheshmani K
dc.publisher.placeMumbai
dc.publisher.universityUniversity of Mumbai
dc.publisher.institutionDepartment of Physics
dc.date.registered
dc.date.completed2008
dc.date.awarded
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Physics

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File251.3 kBAdobe PDFView/Open
02_prelim pages.pdf2.32 MBAdobe PDFView/Open
03_contents.pdf2.63 MBAdobe PDFView/Open
04_chapter 1.pdf4.49 MBAdobe PDFView/Open
05_chapter 2.pdf10.13 MBAdobe PDFView/Open
06_chapter 3.pdf9.48 MBAdobe PDFView/Open
07_chapter 4.pdf7.74 MBAdobe PDFView/Open
08_chapter 5.pdf15.78 MBAdobe PDFView/Open
09_chapter 6.pdf3.54 MBAdobe PDFView/Open
10_chapter 7.pdf1.47 MBAdobe PDFView/Open
11_annexures.pdf799.2 kBAdobe PDFView/Open
80_recommendation.pdf1.72 MBAdobe PDFView/Open


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