Shodhganga : a reservoir of Indian theses @ INFLIBNET
The Shodhganga@INFLIBNET Centre provides a platform for research students to deposit their Ph.D. theses and make it available to the entire scholarly community in open access.
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/532165
| Title: | Design of specific instruction processor using very large scale integration and to study the timing and power analysis of the designed processor |
| Researcher: | Pillai Arun Shridharan Padmavathy |
| Guide(s): | Dubey, Sheshmani K |
| Keywords: | Chip Architecture Debug Module Designed Processor Field Programmable Gate Arrays Performing Arithmetic Physical Sciences Physics Physics Applied |
| University: | University of Mumbai |
| Completed Date: | 2008 |
| Abstract: | newlineNo newline |
| Pagination: | x, 246p |
| URI: | http://hdl.handle.net/10603/532165 |
| Appears in Departments: | Department of Physics |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 01_title.pdf | Attached File | 251.3 kB | Adobe PDF | View/Open |
| 02_prelim pages.pdf | 2.32 MB | Adobe PDF | View/Open | |
| 03_contents.pdf | 2.63 MB | Adobe PDF | View/Open | |
| 04_chapter 1.pdf | 4.49 MB | Adobe PDF | View/Open | |
| 05_chapter 2.pdf | 10.13 MB | Adobe PDF | View/Open | |
| 06_chapter 3.pdf | 9.48 MB | Adobe PDF | View/Open | |
| 07_chapter 4.pdf | 7.74 MB | Adobe PDF | View/Open | |
| 08_chapter 5.pdf | 15.78 MB | Adobe PDF | View/Open | |
| 09_chapter 6.pdf | 3.54 MB | Adobe PDF | View/Open | |
| 10_chapter 7.pdf | 1.47 MB | Adobe PDF | View/Open | |
| 11_annexures.pdf | 799.2 kB | Adobe PDF | View/Open | |
| 80_recommendation.pdf | 1.72 MB | Adobe PDF | View/Open |
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