Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/528370
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dc.coverage.spatialSuperjunction VDMOS
dc.date.accessioned2023-12-06T05:44:53Z-
dc.date.available2023-12-06T05:44:53Z-
dc.identifier.urihttp://hdl.handle.net/10603/528370-
dc.description.abstractPDF attached
dc.format.extentxviii, 101
dc.languageEnglish
dc.relation107
dc.rightsuniversity
dc.titleAnalysis of Superjunction VDMOS Limitations and Solutions
dc.title.alternative
dc.creator.researcherNaugarhiya, Alok
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideKondekar, Pravin N
dc.publisher.placeJabalpur
dc.publisher.universityIndian Institute of Information Technology, Design and Manufacturing, IIITDM Jabalpur
dc.publisher.institutionDepartment of Electronics Communication Engineering
dc.date.registered2011
dc.date.completed2015
dc.date.awarded2015
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics Communication Engineering

Files in This Item:
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01_title.pdfAttached File42.14 kBAdobe PDFView/Open
02_prelim pages.pdf196.44 kBAdobe PDFView/Open
03_table of content.pdf118.92 kBAdobe PDFView/Open
04_abstract.pdf92.15 kBAdobe PDFView/Open
05_chapter 1.pdf215.11 kBAdobe PDFView/Open
06_chapter 2.pdf737.35 kBAdobe PDFView/Open
07_chapter 3.pdf750.46 kBAdobe PDFView/Open
08_chapter 4.pdf608.24 kBAdobe PDFView/Open
09_chapter 5.pdf575.41 kBAdobe PDFView/Open
10_chapter 6.pdf121.11 kBAdobe PDFView/Open
11_annexures.pdf158.98 kBAdobe PDFView/Open
80_recommendation.pdf127.84 kBAdobe PDFView/Open


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