1. Shodhganga@INFLIBNET
  2. Indian Institute of Information Technology, Design and Manufacturing, IIITDM Jabalpur
  3. Department of Electronics Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/528370
Title: Analysis of Superjunction VDMOS Limitations and Solutions
Researcher: Naugarhiya, Alok
Guide(s): Kondekar, Pravin N
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Information Technology, Design and Manufacturing, IIITDM Jabalpur
Completed Date: 2015
Abstract: PDF attached
Pagination: xviii, 101
URI: http://hdl.handle.net/10603/528370
Appears in Departments:Department of Electronics Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File42.14 kBAdobe PDFView/Open
02_prelim pages.pdf196.44 kBAdobe PDFView/Open
03_table of content.pdf118.92 kBAdobe PDFView/Open
04_abstract.pdf92.15 kBAdobe PDFView/Open
05_chapter 1.pdf215.11 kBAdobe PDFView/Open
06_chapter 2.pdf737.35 kBAdobe PDFView/Open
07_chapter 3.pdf750.46 kBAdobe PDFView/Open
08_chapter 4.pdf608.24 kBAdobe PDFView/Open
09_chapter 5.pdf575.41 kBAdobe PDFView/Open
10_chapter 6.pdf121.11 kBAdobe PDFView/Open
11_annexures.pdf158.98 kBAdobe PDFView/Open
80_recommendation.pdf127.84 kBAdobe PDFView/Open
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