Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/526542
Title: Low Leakage Variability Aware Techniques for CMOS Logic Circuits
Researcher: Sharma, Vijay Kumar
Guide(s): Pattanaik, Manisha
Keywords: Computer Science Software Engineering
Engineering
Engineering and Technology
University: Atal Bihari Vajpayee Indian Institute of Information Technology and Management
Completed Date: 2015
Abstract: Attached
Pagination: xxii,205p.
URI: http://hdl.handle.net/10603/526542
Appears in Departments:Department of Electrical and Electronics Engineering

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01_title.pdfAttached File80.36 kBAdobe PDFView/Open
02_prelim pages.pdf139.62 kBAdobe PDFView/Open
03_content.pdf92.02 kBAdobe PDFView/Open
04_abstract.pdf49.59 kBAdobe PDFView/Open
05_chapter 1.pdf99.07 kBAdobe PDFView/Open
06_chapter 2.pdf671.08 kBAdobe PDFView/Open
07_chapter 3.pdf1.37 MBAdobe PDFView/Open
08_chapter 4.pdf3.64 MBAdobe PDFView/Open
09_chapter 5.pdf3.6 MBAdobe PDFView/Open
10_chapter 6.pdf2.78 MBAdobe PDFView/Open
11_annexures.pdf9.24 MBAdobe PDFView/Open
80_recommendation.pdf99.22 kBAdobe PDFView/Open
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