Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/525540
Title: Pipelining strategies for VLSI low power consumption designs
Researcher: Ansiya Eshack
Guide(s): Krishnakumar, S
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Mahatma Gandhi University
Completed Date: 2020
Abstract: newline
Pagination: xxi, 188p.
URI: http://hdl.handle.net/10603/525540
Appears in Departments:School of Technology and Applied Sciences

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File14.26 MBAdobe PDFView/Open
02_prelim pages.pdf5.23 MBAdobe PDFView/Open
03_contents.pdf695.75 kBAdobe PDFView/Open
04_abstract.pdf572.02 kBAdobe PDFView/Open
05_chapter 1.pdf1.16 MBAdobe PDFView/Open
06_chapter 2.pdf927.9 kBAdobe PDFView/Open
07_chapter 3.pdf1.54 MBAdobe PDFView/Open
08_chapter 4.pdf1.2 MBAdobe PDFView/Open
09_chapter 5.pdf846.14 kBAdobe PDFView/Open
10_chapter 6.pdf1.16 MBAdobe PDFView/Open
11_chapter 7.pdf1.15 MBAdobe PDFView/Open
12_annexures.pdf14.5 MBAdobe PDFView/Open
80_recommendation.pdf14.74 MBAdobe PDFView/Open
Show full item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: