Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/524496
Title: | Design and implementation of various topologies of multilevel inverters for enhanced performance |
Researcher: | Vijayaraja L |
Guide(s): | Ganesh Kumar S |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Anna University |
Completed Date: | 2023 |
Abstract: | newline Multilevel Inverters (MLIs) gets attention due to its low electrical stress, common-mode voltage, harmonic distortion, and electromagnetic interference. With fewer components used for construction of MLI, it plays a vital role in applications such as electric vehicles, renewable energy systems and High Voltage Direct Current (HVDC) transmission systems. In this work, a detailed survey is made on the multilevel inverters to find its suitability for particular applications. Research is performed on various types of MLIs such as symmetric, asymmetric, hybrid and modularized multilevel inverters for identifying the issues in generating more levels at the output and to construct more voltage levels using fewer components. A summary of various issues in multilevel inverters with reduced switch count is provided, so that a novel topology of multilevel inverters can be designed. From the study, it is decided to design a multilevel inverter to construct more voltage levels with fewer components. In this thesis, the following four structures are proposed, compared with other existing structures, analyzed, simulated and experimentally tested: newline1. MLI with and without series diode connection. newline2. MLI with and without cross connecting switches. newlineIn MLI with series diode configuration, a tri-state inverter which could generate three direct current (D.C) voltage levels. Cascading such five tri-state architectures with H- bridge circuit generate 485 voltage levels. Algorithms to design the amplitude of voltage sources and the generation of pulses are discussed. In order to drive a high inductive load, a diode is connected in series with the power switches of the proposed tri-state architecture. Simulation study and real time testing are completed for a single-phase 485-level inverter. newline |
Pagination: | xxiii,193p |
URI: | http://hdl.handle.net/10603/524496 |
Appears in Departments: | Faculty of Electrical Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 98.13 kB | Adobe PDF | View/Open |
02_prelim.pdf | 2.37 MB | Adobe PDF | View/Open | |
03_content.pdf | 281.29 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 145.14 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 1.03 MB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 1.62 MB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 2.48 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 2.55 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 2.08 MB | Adobe PDF | View/Open | |
10_annexures.pdf | 165.14 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 132 kB | Adobe PDF | View/Open |
Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).
Altmetric Badge: