Design and Analysis of Structurally Engineered Junctionless Field Effect Transistor

Abstract

The development of smart computing devices has evolved due to the relentless scaling of conventional MOSFETs. In the nanoscale regime, the MOSFET scaling has reached a physical limit owing to the increased short-channel effects. To unravel the issue of rising short-channel effects the multigate MOSFETs and high-k dielectric materials have been introduced. Nevertheless, the realization of multigate MOSFETs with short-channel dimensions becomes extremely challenging due to the ultra-steep doping concentration gradient at p-n junctions. The fabrication of these ultra-steep p-n junctions has been avoided in the junctionless FET (JLFET) which reflects lesser leakage current and smaller thermal budget in comparison to the conventional multigate MOSFETs. However, as the channel length approaches to sub-20 nm region, the performance of JLFETs degrades too due to poor channel depletion which leads to increased OFF-state leakage current and hence, high static power dissipation with immoderate short-channel effects. Therefore, this thesis addresses this vital issue of increased OFF-state current in JLFETs by proposing a recessed double gate JLFET (R_DGJLFET) with improved electrical performance. By employing the gate electrode over the recessed silicon channel, a remarkable performance improvement has been achieved with smaller OFF-state leakage current, better ON-to-OFF current ratio, steeper subthreshold slope, and lesser drain-induced-barrier-lowering. It has been investigated that the proposed R_DGJLFET maintains its performance edge over the conventional counterpart in terms of channel length scaling. The depth and length of the recessed silicon channel have been found as the additional performance tuning parameters. In comparison to conventional double gate JLFET (C_DGJLFET), the proposed device offers similar electrical performance with a larger effective oxide thickness. Additionally, the device reflects optimum and robust performance with smaller variations in subthreshold slope within a range of gate work function