Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/522928
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-11-03T06:56:33Z-
dc.date.available2023-11-03T06:56:33Z-
dc.identifier.urihttp://hdl.handle.net/10603/522928-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleAutomating UVM Based Functional And Design Verification For SOC Using Intelligent Algorithm
dc.title.alternative
dc.creator.researcherN. Bhuvaneswary
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideJ. Deny
dc.publisher.placeVirudhunagar
dc.publisher.universityKalasalingam University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2018
dc.date.completed2023
dc.date.awarded2023
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
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01_title.pdf.pdfAttached File28.93 kBAdobe PDFView/Open
02_prelim pages.pdf1.64 MBAdobe PDFView/Open
03_content.pdf40.28 kBAdobe PDFView/Open
04_abstract.pdf99.82 kBAdobe PDFView/Open
05_chapter 1.pdf195.34 kBAdobe PDFView/Open
06_chapter 2.pdf223.1 kBAdobe PDFView/Open
07_chapter 3.pdf441.54 kBAdobe PDFView/Open
08_chapter 4.pdf219.44 kBAdobe PDFView/Open
09_chapter 5.pdf320.51 kBAdobe PDFView/Open
10_annexures.pdf206.08 kBAdobe PDFView/Open
11_chapter 6.pdf639.97 kBAdobe PDFView/Open
12_chapter 7.pdf133.81 kBAdobe PDFView/Open
80_recommendation.pdf157.16 kBAdobe PDFView/Open


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