Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/522928
Title: Automating UVM Based Functional And Design Verification For SOC Using Intelligent Algorithm
Researcher: N. Bhuvaneswary
Guide(s): J. Deny
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Kalasalingam University
Completed Date: 2023
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/522928
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdf.pdfAttached File28.93 kBAdobe PDFView/Open
02_prelim pages.pdf1.64 MBAdobe PDFView/Open
03_content.pdf40.28 kBAdobe PDFView/Open
04_abstract.pdf99.82 kBAdobe PDFView/Open
05_chapter 1.pdf195.34 kBAdobe PDFView/Open
06_chapter 2.pdf223.1 kBAdobe PDFView/Open
07_chapter 3.pdf441.54 kBAdobe PDFView/Open
08_chapter 4.pdf219.44 kBAdobe PDFView/Open
09_chapter 5.pdf320.51 kBAdobe PDFView/Open
10_annexures.pdf206.08 kBAdobe PDFView/Open
11_chapter 6.pdf639.97 kBAdobe PDFView/Open
12_chapter 7.pdf133.81 kBAdobe PDFView/Open
80_recommendation.pdf157.16 kBAdobe PDFView/Open
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