Finfet and cntfet device based acs architecture for low power viterbi decoder using asynchronous techniques for digital communication systems

Abstract

Recent world uses updated integrated modules based on ASICs and SOCs. The ASICs and SOCs are provides minimum power consumption, high speed and lesser area utilization as well. The Power consumption factor and current driving ability are related to each other. The current driving ability can be improved with CMOS technology. But CMOS suffers with leakage and short channel effects when it was scaled below 45nm. Alternate solutions such as minimum-temperature CMOS, double-gate MOSFETand#8223;s and Carbon nanotubes are utilized in most of the components. newlineChapter-1: This chapter gives a brief introduction about the ACS Architecture for Low Power Viterbi Decoder design, problem definition and motivation of the research work, research contribution, objective and expected outcomes. Chapter-2: In this chapter, we have discussed about literature survey regarding the various methods, circuits and devices used in the design of ACS Architecture for Low Power Viterbi Decoder. It describes the Convolutional coding structure and its properties. Trellis tree diagram representation and Performance parameters of Convolutional code. Basic concepts related to the Viterbi algorithm, such as hard/soft-decision decoding, etc., are also introduced in this chapter. Chapter-3: gives the detailed implementation of the ACS block in Viterbi algorithm using CMOS devices. A brief description of four methods are investigated in this chapter. Chapter-4: In this chapter we provide the details of the proposed CNTFET based design. All the results and proofs of the proposed method is presented. The comparison with CMOS and FinFET is done newline newline