Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/522082
Title: Design of energy efficient high speed nanoscale logic circuits with soft error tolerance
Researcher: Ranjani Aruna A
Guide(s): Kamala J
Keywords: Computer Science
Computer Science Information Systems
Engineering and Technology
High Speed Nanoscale
Nanomolecular
Spintronics A
University: Anna University
Completed Date: 2023
Abstract: newline Modern computing systems endure leakage power, short channel effects, and performance instability of deep-sub micrometer Complementary Metal Oxide Silicon (CMOS) technology. Scaling factor is an essential feature of CMOS technology. It faces several challenges with traditional CMOS technology. Designers focus on performance improvement in-terms of lower energy consumption, area, and high-speed devices. To resolve the problems, alternative spintronics and quantum nanomolecular devices are designed. This research proposes design of combinational and sequential circuits using novel nano devices. Spintronics devices have been chosen for the realization of combinational circuits. Introducing clock to the spintronics circuits is not feasible, so quantum cells have been chosen to realize the sequential circuits. Nanostructure Magnetic Tunnel Junction (MTJ) is one type of spintronics device. The structure of MTJ has a heavy metal that stacks the three-layer structure. An insulating layer (MgO) is sandwiched between two ferromagnetic (CoFeB) layers. One ferromagnetic layer is fixed or pinned; another one is a free layer. Input can be stored in MTJ, as a nonvolatile data using a writing circuit. Spin Orbit Torque (SOT) and Spin Transfer Torque (STT) switching mechanisms are used in 3-terminal Perpendicular Magnetic Tunnel Junction (PMTJ). The SOT switching is faster compared to the other switching circuits. Free layer spin electrons are aligned perpendicular to the external electric field. The non-volatile data storage is faster. It supports separate paths for read and write operations. Hence it is chosen for the research process. This research proposes Read Write Parallel Switching (RWPS) technique using SOT based writing circuit. The nonvolatile data is stored in MZ direction when external current pulse is greater than or equal to the critical charge value. RWPS-SOT writing speed is 64% iv faster than STT switching circuit. MTJ accesses the input data at a frequency of 100 MHz. Logic gates and Full Adder
Pagination: xx, 137 p.
URI: http://hdl.handle.net/10603/522082
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File25.72 kBAdobe PDFView/Open
02_prelim_pages.pdf511.86 kBAdobe PDFView/Open
03_content.pdf94.36 kBAdobe PDFView/Open
04_abstract.pdf12.88 kBAdobe PDFView/Open
05_chapter 1.pdf550.25 kBAdobe PDFView/Open
06_chapter 2.pdf327.47 kBAdobe PDFView/Open
07_chapter 3.pdf4.59 MBAdobe PDFView/Open
08_chapter 4.pdf3.07 MBAdobe PDFView/Open
09_chapter 5.pdf5.48 MBAdobe PDFView/Open
10_chapter 6.pdf3.62 MBAdobe PDFView/Open
11_annexures.pdf113.54 kBAdobe PDFView/Open
80_recommendation.pdf87.77 kBAdobe PDFView/Open
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