Certain investigations and performance analysis on area efficient low power VLSI implementation of fir filter

Abstract

newline Finite Impulse Response (FIR) filters are essential tools in image processing applications, as they help to generate high-quality noise-free images in imaging equipment. These filters are created using a combination of adders, multipliers, and delay units that are designed to optimize power consumption and performance. Despite their benefits, FIR filters that utilize DADDA multipliers and booth multiplier-based designs are prone to issues such as coefficient alignment and lengthy computation times. To address these challenges, this research proposes novel FIR filter designs that aim to minimize power consumption, area, and latency of the VLSI circuit for medical imaging applications. The research is divided into three phases, where each phase presents a new strategy to analyze the filtering performance for 4- tap to 32-tap filter designs. The first phase introduces the Modified Carry Save Adder (MCSA), which utilizes Ripple Carry Adder (RCA) logic to reduce delay and power consumption. However, the proposed FIR filter architecture uses a large number of adders, resulting in a high-power consumption problem. In the second phase, the Modified Vedic Multiplier and Carry Look-Ahead Adder (CLA) logic are incorporated into the 32-tap FIR filter construction. The Speculative Brent Kung adder reduces the number of adders in the Vedic Multiplier, while the Carry Look-Ahead (CLA) Adder employs Partial Full (PFA) Adder logic to minimize power consumption. Although this FIR filter performs well in all areas, its precision deteriorates over time due to circuit aging.