Design and analysis of high speed arithmetic circuits and multi operand adders for DSP application

Abstract

newline Binary Tree Adder (BTA) is considered as a simple Multi-Operand Adders (MOA) that adds multiple operands with the aid of two operand units in the binary tree structure. The performance of this MOA is mainly affected by the delay and area performance of the adders employed in this configuration. The objective of this research work is to design and analysis high speed adders and multipliers for various signal processing applications. Hence optimization of adders and multipliers in terms of delay, area and power is to be pursued. To meet this requirement different types of binary tree adders like RCA, Carry Increment Adder, Sklansky Adder, Kogge Stone Adder, Brent Kung Adder, Carry Skip Adder and Carry Select Adder and different types of multipliers like Vedic Multiplier, Wallace Tree Multiplier, Vedic-Wallace Tree Multiplier, Booth Multiplier and Modified Booth are taken in to account. The next objective of this research work is to design delay efficient 16-tap FIR filter and high speed 16-bit MAC unit for various signal applications. Each adder, multiplier, divider, FIR filter and MAC unit are simulated and synthesized using 90nm Cadence EDA tool.