Certain investigations on performance of scheduling algorithms in network on chip

Abstract

A Multi-Processor System on Chip (MPSoC) is a high-performance newlineprocessing system that consists of a multicore application, real-time newlineprocessors, a specialized graphics core, and programmable logic. MPSoCs newlineand Chip Multi Processors (CMPs) have hundreds or thousands of cores to newlinecomplete the task efficiently. The transportation of the data between the cores newlineon the chip is performed by high-performance interconnections. A bus newlineinterface connects components of the traditional system with the connectivity newlinebackbone. The On-chip bus or a multilayer bus design is used as the newlineconnecting backbone. The bus design of the Many-core architectures newlinedegrades the performance of the On-Chip connectivity framework when the newlinenumber of cores increases. newlineThe complexity of each component in a system grows fast as the newlinedensity of very-large-scale integration design increases. MPSoC and CMP newlinearchitectures use the bus structures for on-chip communication and integrate newlinethe complex heterogeneous functional elements. Traditional bus-based newlinecommunication techniques lack scalability, predictability, performance newlineimprovement, power, timing closure, scalability, and other needs of future newlineSystem on Chip (SoC). To overcome the limitations of the MPSoC and CMP newlinearchitectures, an organized and scalable connectivity architecture, Network on newlineChip (NoC), has been proposed to minimize the complexity of the On-chip newlinecommunication problem, to address the design productivity and signal newlineintegrity requirements of next-generation system designs. newline