Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/520114
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dc.coverage.spatialDesign and implementation of efficient approximate multipliers for digital image processing
dc.date.accessioned2023-10-22T08:17:13Z-
dc.date.available2023-10-22T08:17:13Z-
dc.identifier.urihttp://hdl.handle.net/10603/520114-
dc.description.abstractArithmetic and Logic Unit (ALU) is the essential component of digital newlinesignal and image processing systems. Adders and multipliers are the essential newlinecomponents in design of digital processing hardware. However, the multiplier newlineis the significant element that contributes for the total delay and hardware newlinecomplexity in Complementary Metal Oxide Semiconductor (CMOS) newlinehardware design. Hence in this research, an effort is made to design novel newlinearchitectures for multiplier using approximate computing targeting error newlineresilient applications in digital image and signal processing. The proposed newlineapproach concentrates on multiplication algorithm modeling, architecture newlinedesign using Hardware Description Language (HDL) model, functional and newlineperformance analysis, and driving capability and novelty verification through newlinereal time implementations. newlineA low power area efficient approximate multiplier that uses two new newlinevariants of 4:2 approximate compressors for Partial Product (PP) newlineaccumulation is proposed. The proposed compressor 1 designated as PC-1 newlinegenerates minimal error compared to prior approaches and the proposed newlinecompressor-2 designated as PC-2 demonstrates fewer gate count when newlinecompared to PC-1 and other prior designs. The multiplier performs PP newlinecompression in stages using Carry save addition with dadda structure based newlinePP arrangement. In the final stage, the PPs are reduced into two rows of sum newlineand carry signals and are added using Ripple Carry Adder (RCA). newline
dc.format.extentxix,126p.
dc.languageEnglish
dc.relationp.121-125
dc.rightsuniversity
dc.titleDesign and implementation of efficient approximate multipliers for digital image processing
dc.title.alternative
dc.creator.researcherNagarajan, S
dc.subject.keywordArithmetic and Logic Unit
dc.subject.keywordComplementary Metal Oxide Semiconductor
dc.subject.keywordComputer Science
dc.subject.keywordComputer Science Information Systems
dc.subject.keywordDigital Image Processing
dc.subject.keywordEngineering and Technology
dc.description.note
dc.contributor.guide
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registered
dc.date.completed2022
dc.date.awarded2022
dc.format.dimensions21 c m
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File74.74 kBAdobe PDFView/Open
02_prelim pages.pdf1.63 MBAdobe PDFView/Open
03_content.pdf133.12 kBAdobe PDFView/Open
04_abstract.pdf99.02 kBAdobe PDFView/Open
05_chapter 1.pdf216.08 kBAdobe PDFView/Open
06_chapter 2.pdf194.02 kBAdobe PDFView/Open
07_chapter 3.pdf1.2 MBAdobe PDFView/Open
08_chapter 4.pdf912.53 kBAdobe PDFView/Open
09_chapter 5.pdf909.56 kBAdobe PDFView/Open
10_chapter 6.pdf3.37 MBAdobe PDFView/Open
11_annexures.pdf84.66 kBAdobe PDFView/Open
80_recommendation.pdf137.31 kBAdobe PDFView/Open


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